1. Field of Invention
The present invention relates to a phase-locked loop. More particularly, the present invention relates to a phase-locked loop having a function of automatic parameter adjustment.
2. Description of Related Art
A phase-locked loop (PLL) is a loop system for comparing output and input phases. Currently, the concept of phase locking has been applied in the electronic and communication fields extensively. The application of the PLL includes a frequency modulation (FM) and amplitude modulation (AM) demodulation apparatus, a frequency synthesizer, a frequency doubler, and a clock recovery circuits, etc.
FIG. 1 is a schematic view of the basic architecture of a conventional PLL. A PLL 100 includes a phase comparator 101, a charging/discharging unit 103, a low pass filter 105, a voltage-controlled oscillator 107, and a feedback unit 109. In the operation process of a normal PLL, the frequency is acquired first, and the internal frequency will be increased to 90% of the target frequency. After the difference between the internal frequency and the target frequency is within 10%, the phase-locking step is entered. Then, the phase is acquired, and the phase and frequency are locked eventually. As different locked frequencies have different control voltages, the PLL has different loop control parameters respectively, thus influencing the stability.
In order to stabilize the output frequency, a conventional method involves adding an analog-to-digital converter first. The analog-to-digital converter is connected to the low pass filter to detect the voltage on the low pass filter. Then, after the values output from the analog-to-digital converter are determined by a processor, a group of data is output to a digital-to-analog converter to be converted into an analog signal, so as to directly control the analog portion of the PLL. Otherwise, the loop parameters of the voltage-controlled oscillator or other parts are modulated directly by using the control signal output from the processor, such that the stability of the loop remains consistent, thereby achieving the optimization. The details of this method are described in U.S. Pat. No. 6,661,267 B2.
Another method involves adding an analog-to-digital converter to the low pass filter to detect the control voltage, and additionally adding a digital frequency detector to detect the output frequency. The two detection results are determined by a processor, and then a group of control signals is output to modulate the voltage-controlled oscillator or other loop parameters. The details of this method are described in U.S. Pat. No. 6,426,680 B1.
However, although the stability of the output frequency is improved through automatic adjustment of the PLL in the conventional art described above, as the analog-to-digital converter and complicated digital controller are added, the chip area and the power consumption increases, which leads to a high cost, low competitiveness, and complexity of the design.